With the rapid development of semiconductor manufacturing technology, semiconductor devices are now moving towards the direction of higher element density and higher integration degree. As the most fundamental semiconductor device, transistor is currently being widely used. Along with the improvement of the element density and the integrity of semiconductor devices, the dimensions of the gate in transistors thus become much shorter than in the past. However, a shorter gate in a transistor may cause short channel effect, thus leads to a leakage current in the transistor and eventually affects the electrical properties of the semiconductor device. Currently, improving the properties of semiconductor devices in the present technology is mainly through the improvement of the mobility of carriers. As the mobility of carriers increases, the driving current of the transistor increases, thus the leakage current in the transistor decreases. Furthermore, a key factor to improve the mobility of carriers is to increase the stress in the channel region of the transistor, therefore improving the stress in the channel region of a transistor may significantly improve the performance of the transistor.
An existing method to improve the stress in the channel region of a transistor is to form a stress layer in the source region and the drain region of the transistor. Specifically, the stress layer in a p-type metal-oxide semiconductor (PMOS) transistor may be made of SiGe. Because SiGe and Si have the same lattice structure, i.e., the ‘diamond’ structure, and, at room temperature, the lattice constant of SiGe is larger than that of Si there is a lattice mismatch between Si and SiGe. Such a lattice mismatch ensures that the stress layer provides compressive stress in the channel region and further improves the mobility of the carriers in the channel region of the PMOS transistor. Accordingly, the stress layer in an n-type metal-oxide semiconductor (NMOS) transistor may be made of SiC. At room temperature, the lattice constant of SiC is smaller than that of Si, therefore the lattice mismatch between Si and SiC leads to tensile stress in the channel region and further improves the performance of the NMOS transistor.
However, for transistors fabricated by using the existing method with a stress layer formed in the source region and the drain region, the structural appearance of the transistor may be poor and the performance may be unstable. Specifically, following an existing method, EPI particles, also known as mushroom defects, are often formed on the surface of the semiconductor device close to the gate, which may cause a leakage current on the top of the gate layer or the subsequently-formed metal gate. Thus, the performance of the transistor may be unstable, the reliability may be low, and the yield may also decrease.
The disclosed methods and structures are directed to solve one or more problems set forth above and other problems.